8086 Microprocessor
Final Revision, Lectures 9–14

What is a bus cycle

The 8086 executes a bus cycle to transfer data or fetch an instruction over the system bus. The minimum bus cycle is 4 clock periods (T-states): T1–T4. Slower devices force extra wait states, Tw, inserted between T3 and T4. Every bus cycle follows the same shape: address out → read/write + control signals → data transfer → termination.

Read cycle

Control pins

T-state breakdown — Read

1. T1: 20-bit address placed on AD15–AD0 and A16/S3–A19/S6. Processor outputs LOW on DT/R (holds until T4).
2. T2: AD15–AD0 lines go tri-state. A16/S3–A19/S6 switch from address to status S3–S6. RD and DEN go LOW (hold until T4).
3. T3 / T_w: Data comes in on AD15–AD0 from memory/device. If the device pulls READY LOW at the start of T3, the CPU inserts wait states (T_w) until READY goes HIGH. Data is latched at the end of this state.
4. T4: Command lines disabled — bus cycle terminates.

Write cycle

Same shape as the read cycle, with two differences: the WR pin replaces RD, and DT/R is driven HIGH throughout (CPU is transmitting, not receiving).

T-state breakdown — Write

1. T1: 20-bit address on AD15–AD0 / A16–A19. DT/R goes HIGH, holds until T4.
2. T2: AD lines tri-state, address/status lines switch to S3–S6. WR and DEN go LOW (hold until T4).
3. T3 / T_w: Data goes OUT from CPU to memory/device on AD15–AD0. Wait states inserted the same way as the read cycle if READY is pulled LOW.
4. T4: Command lines disabled — bus cycle terminates.

Memory space: even/odd banking

8086 memory is split into two banks, up to 512K bytes each: the odd bank (connects to D15–D8) and the even bank (connects to D7–D0). Bank selection is controlled by BHE and A0:

Worked examples

MOV DH, [BX] — byte operation, address 20004H (even): A0=LOW, BHE=HIGH → even bank selected → byte comes off D7–D0 → DH. Single bus cycle.

MOV DH, [BX] — byte operation, address 20005H (odd): A0=HIGH, BHE=LOW → odd bank selected → byte comes off D15–D8 → DH. Single bus cycle.

MOV [BX], CX — word operation, address 20008H (even): A0=LOW, BHE=LOW → both banks selected → CL on D7–D0, CH on D15–D8, written to 20008H/20009H. Single bus cycle.

MOV [BX], CX — word operation, address 20007H (odd): needs two bus cycles. Cycle 1: A0=HIGH, BHE=LOW → odd bank → CL written to 20007H. Cycle 2: A0=LOW, BHE=HIGH → even bank → CH written to 20008H.

The interrupt system lets the processor handle unusual circumstances and lets external hardware communicate with it, without the CPU wasting cycles constantly checking devices. Three categories: predefined interrupts, software interrupts (user-defined), and hardware interrupts (user-defined).

Polling vs. interrupt-driven I/O

Polling: the main program periodically breaks away (e.g. every 20 ms) to run the keyboard driver and check the device directly — it "asks" the keyboard every cycle whether it has data, whether or not it actually does. This wastes CPU time on empty checks.

Interrupt-driven: the keyboard itself signals the interrupt controller only when it actually has data, which triggers the appropriate ISR. The CPU runs the main program uninterrupted otherwise — no wasted checks.

Interrupt vector table

Every 8086 interrupt has a service routine. Their addresses live in a table in 0000:0000H–0000:03FFH. Each interrupt gets 4 bytes (2 for IP, 2 for CS) → the table holds 256 vectors total, one per interrupt type code (0–255).

Worked example — INT 2: IP is stored at table address 4×2 = 00008H; CS is stored at 4×2+2 = 0000AH. The processor reads both values, then computes the ISR's physical start address as CS×10H + IP.

Response to an interrupt — the 8 steps

1. Push the existing Flag register, CS, and IP onto the stack.
2. Jump to the interrupt vector table.
3. Find the appropriate CS and IP in the vector table.
4. Load the new CS and IP for the Interrupt Service Routine.
5. Execute the Interrupt Service Routine.
6. Pop the IP, CS, and Flag of the main program (via the ISR's final IRET).
7. Load the popped IP, CS, and Flag.
8. Resume executing the main program.

Along the way, TF and IF are cleared when the interrupt is taken, so the ISR itself isn't interrupted by single-stepping or another maskable interrupt unless it re-enables them.

Interrupt priority

The 256 interrupts & predefined types 0–4

Types 5–31 and 32–255

Non-maskable interrupt (NMI) — use cases

INTA sequence (for maskable / INTR-driven interrupts)

The interrupt-acknowledge sequence has two INTA bus cycles:

1. ALE is issued, loading the address latches with indeterminate information.
2. The first INTA cycle tells the requesting hardware that acknowledgment is in progress and to get ready.
3. On the second INTA cycle, the hardware places its interrupt type code (32–255) onto the low data bus lines.

Instruction processing has three basic steps: (1) fetch from memory, (2) decode, (3) execute (often needs another memory access for operands/results). Memory interfacing is about connecting memory chips to the microprocessor and reading/writing them correctly.

ROM family (PROM → EPROM → EEPROM)

SRAM vs. DRAM

DRAM types

• SDRAM — synchronizes memory speed with the CPU clock; up to 133 MHz.
• RDRAM (Rambus) — popular early-2000s, video/graphics cards; up to 1 GHz.
• DDR SDRAM — "double pumping": transfers data on both the rising and falling clock edges, nearly doubling bandwidth at the same clock frequency.
• DDR1→DDR2→DDR3→DDR4 — each generation faster, but not backward-compatible. DDR4 reaches 2133/2400/2666/3200 MT/s.

DRAM packaging

Memory interface — the three buses

A 16-bit memory word is split into high and low 8-bit banks, connected to the upper/lower halves of the data bus and selected by BHE/A0 — same logic as Lecture 9's memory banking.

ROM/EPROM vs. SRAM interfacing

• ROM/EPROM (read-only): don't need BHE/A0 at all. Address line A1-and-up connect straight to the processor's address lines; unused address lines are repurposed for chip select. They have an output-enable pin to interface with the multiplexed bus.
• Static RAM (read/write): does use BHE and A0 in its chip-select logic. Data lines connect to either AD15–AD8 or AD7–AD0. A decoder selects which RAM chip is active.

The 8205 decoder

The Intel 8205 is a common decoder for this: 3 enables (E1, E2, E3), 3 inputs (A0–A2), and 8 outputs — enough to select up to 8 RAM chips (e.g. the 2142).

Two methods exist for interfacing I/O devices to a microprocessor: memory-mapped I/O and I/O-mapped (isolated) I/O. The 8086/8088 (and most Intel µPs) use isolated I/O; the 68HC11 is the course's example of memory-mapped I/O.

Memory-mapped vs. I/O-mapped — the class comparison table

Memory-mapped I/O

The I/O device is treated as an ordinary memory location — the same instructions (e.g. MOV) that access memory also access the device. Advantage: no extra instructions or control circuitry needed. Disadvantage: eats into the address space available to actual memory. Used by the 68HC11.

I/O-mapped (isolated) I/O

I/O addresses live in a separate address space from memory, reached only through dedicated port instructions. Advantage: memory keeps its full addressable space. Disadvantage: needs specific instructions and separate control signals — IOR to read from an I/O device, IOW to write to one.

The M/IO pin

The processor tells memory and I/O apart using the M/IO pin: pulled one way for a MOV (memory) instruction, the other way for an IN/OUT (I/O) instruction.

I/O ports — IN / OUT

• IN receives data from a specified port into the accumulator (AL, AH, or AX).
• OUT sends data from the accumulator to a specified port.
• Original IBM PC: 8-bit port addresses — 256 ports, 00h–FFh.
• Newer machines: 16-bit port addresses — 65,536 ports, 0000h–FFFFh.

8-bit port: address is encoded directly in the instruction (1 byte opcode + 1 byte address), carried on A0–A7. No segment register involved.

16-bit port: address must be loaded into DX first, carried on A0–A15. Still no segment register.

Transfer width: 8-bit transfers use AL; 16-bit transfers use the full AX (low byte AL → specified port, high byte AH → the next port address — little endian).

Worked assembly example (Slide 13)

An 8088 system monitors a critical temperature at input port 22h, and raises an alarm if it hits 100:

Chk:  IN   AL, 22h    ; Read temperature from port 22h
      CMP  AL, 100    ; Is it >= 100?
      JB   Chk        ; If not, keep monitoring
      CALL Alarm      ; If it is, set off alarm

The 74LS245 octal bus transceiver

A common example ties switches to the 8086 through a 74LS245 — an octal bidirectional buffer/transceiver. Its DIR pin sets transfer direction, and its CS is generated by decoding the address lines together with IORD. Data moves over D0–D7; the I/O control signal (IORD) confirms the access is I/O-mapped, not memory.

Processor family lineage covered: 8085 → 8086 → 186 → 286 → 386 → 486 → 586 (P1–P4, Core 2 Duo → Core i7).

Pipelined vs. unpipelined execution

Unpipelined: each job (fetch → decode → execute) starts and fully finishes before the next job begins — jobs run one after another, back to back.

Pipelined: each job is broken into smaller stages (FET, DEC, EXE). While instruction I1 is in its EXE stage, I2 can already be in DEC, and I3 can already be in FET — stages overlap across a clock cycle, so throughput goes up even though any single instruction still takes 3 stages to finish.

Multi-core: what and why

A multi-core processor is a single component with two or more independent CPU cores that each read and execute ordinary instructions (add, move, branch). Multiple cores run multiple instructions at the same time, boosting throughput for parallel-friendly programs. Cores are usually integrated onto one die (a chip multiprocessor, CMP) or onto multiple dies in one package. Within each core, threads are still time-sliced, same as on a single-core processor.

Why go multi-core?

• Pushing single-core clock frequency higher runs into heat, speed-of-light propagation limits, and hard design/verification problems.
• Deeply pipelined circuits need large design teams and expensive cooling infrastructure at scale (server farms).
• Many modern applications are already multithreaded.
• General industry trend: shift toward parallelism rather than raw clock speed.

Processor family: i3 / i5 / i7

Cache: larger L3 cache speeds up repetitive tasks and multitasking — background tasks stay "ready" in cache when you switch windows. Desktop i5: 3–8 MB L3. Desktop i7: 8–15 MB L3.

Turbo Boost

Intel's built-in "overclocking" feature: lets the processor exceed its base clock speed when only one or two cores are actually needed (e.g. a demanding single-threaded task), by effectively powering down unused cores. Both Core i5 and Core i7 support Turbo Boost; it's activated when the OS requests the highest performance state, and its frequency ceiling is highest on Core i7.

Note the pattern: base frequency stays fixed at 1.73 GHz regardless of how many cores are active, but the fewer cores in use, the higher Turbo Boost can push the active core(s).

Hyper-Threading

Intel Hyper-Threading uses multi-threading so a processor appears to have more cores than it physically does, to the OS and applications — useful for multitasking, multimedia transcoding/rendering, and web loads with several simultaneous elements.

Integrated graphics

Graphics built directly into the processor core (rather than the motherboard chipset, as in older designs). Saves power since there's no separate graphics chip drawing current on the board.

Updated microprocessors used in 2026

Precision Boost Overdrive (PBO) — AMD Ryzen

What it is: a Ryzen feature that pushes CPU frequency higher than stock boost, in real time, without manual overclocking — as long as cooling is sufficient.

How it works: increases voltage and wattage to extract more performance within the thermal limits available, going beyond default power limits. Easier to use than manual overclocking, though manual OC can still edge out slightly higher performance.

Getting the most from it: pair PBO with AMD's Curve Optimizer (CO) to adjust the voltage-frequency curve per core (or all cores) — effectively undervolting to reach higher frequencies within thermal limits.

Why DMA?

Programmed I/O and interrupt-driven I/O both need active CPU involvement, which caps the transfer rate and ties up the CPU. Programmed I/O gets high transfer rates but the CPU does nothing else meanwhile; interrupt I/O frees the CPU somewhat but at the cost of transfer rate. DMA (Direct Memory Access) solves both: an extra hardware module moves data directly between memory and I/O, without routing it through the processor.

DMA function

The DMA controller is an additional module on the system bus. It takes over from the CPU for I/O transfers, and must either wait to use the bus only when the CPU doesn't need it, or force the CPU to briefly suspend operation.

What the CPU tells the DMA controller (once, up front)

• Read or write
• Device address
• Starting address of the memory block
• Amount of data to transfer

After that, the CPU carries on with other work. The DMA module transfers data one word at a time, directly to/from memory, and interrupts the CPU only once — when the whole transfer is finished. So the CPU is involved only twice: at the start and at the end.

The 8-step DMA transfer sequence

1. µP initializes the DMAC by giving it the starting address and the number of bytes to transfer.
2. An I/O device requests the DMAC to perform a DMA transfer, through the DREQ line.
3. The DMAC in turn sends a request signal to the µP, through the HOLD line.
4. The µP finishes its current machine cycle and releases the system bus (disconnects from it), and acknowledges the HOLD signal through the HLDA line.
5. The DMAC acquires control of the system bus, and sends the DACK signal to the I/O peripheral — the DMA transfer begins.
6. After every byte transferred, the Address register is incremented (or decremented) and the Count register is decremented.
7. This continues until the Count reaches zero (Terminal Count) — the DMA transfer is now complete.
8. At the end, the DMAC releases the system bus by setting HOLD = 0. The µP takes back control of the system bus and continues its own operation.

DMA module diagram

Internally, the module holds a Data Count register, a Data Register, an Address Register, and Control Logic that manages the DMA Request/Acknowledge handshake, raises an interrupt when done, and drives Read/Write.

Intel 8237 DMA controller — key signals

Devices that typically use DMA: floppy drive, hard drive, sound card.

DMA bus configurations

Microcontroller concepts

Microprocessor — a processing unit with basic I/O interfacing and off-chip memory (e.g. 8008, 8080, 8086, 80286, Pentium).

Single-chip microcomputer — a processing unit with on-chip memory, I/O devices, and often extra peripherals like timers and A/D converters (e.g. Intel 8048, 8051, Motorola 68HC11/12).

Microcontroller — an I/O-oriented single-chip microcomputer, distinguished from other single-chip microcomputers by:

• Extended I/O: sync/async communication devices, A/D and D/A converters, timers, counters, watchdogs.
• Interrupt handling: more levels of interrupt priority, and the ability to mask individual interrupts.
• Instruction set: instructions oriented toward bit-manipulation — operating on single bits of memory words or I/O ports.